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1

[IEEE 2002 IEEE International Symposium on Circuits and Systems - Phoenix-Scottsdale, AZ, USA (26-29 May 2002)] 2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353) - High-speed and low-power cellular non-linear networks using single-electron tunneling technology

Gerousis, C., Goodnick, S.M., Porod, W., Csurgay, A.I.

Year:

2002

Language:

english

File:

PDF, 360 KB

english, 2002

2

[Presses Polytech. Univ. Romandes ISCAS 2000 Geneva. 2000 IEEE International Symposium on Circuits and Systems. Emerging Technologies for the 21st Century. Proceedings - Geneva, Switzerland (28-31 May 2000)] 2000 IEEE International Symposium on Circuits and Systems. Emerging Technologies for the 21st Century. Proceedings (IEEE Cat No.00CH36353) - Modeling nanoelectronic CNN cells: CMOS, SETs and QCAs

Gerousis, C., Goodnick, S.M., Xiaohui Wang,, Porod, W., Csurgay, A.I., Toth, G., Lent, C.S.

Year:

2000

Language:

english

File:

PDF, 94 KB

english, 2000

3

SPIE Proceedings [SPIE SPIE Advanced Lithography - San Jose, California, United States (Sunday 26 February 2017)] Design-Process-Technology Co-optimization for Manufacturability XI - Exploiting regularity: breakthroughs in sub-7nm place-and-route

Capodieci, Luigi, Cain, Jason P., Liebmann, L., Gerousis, V., Gutwin, Paul, Zhu, Xuelian, Petykiewicz, Jan

Year:

2017

Language:

english

File:

PDF, 4.81 MB

english, 2017

4

Toward nanoelectronic cellular neural networks

C. Gerousis, S. M. Goodnick, W. Porod

Journal:

International Journal of Circuit Theory and Applications

Year:

2000

Language:

english

File:

PDF, 353 KB

english, 2000

5

Simulation of Single-Electron Tunneling Circuits

C.P. Gerousis, S.M. Goodnick

Journal:

physica status solidi (b)

Year:

2002

Language:

english

File:

PDF, 280 KB

english, 2002

6

Nanoelectronic single-electron transistor circuits and architectures

C. P. Gerousis, S. M. Goodnick, W. Porod

Journal:

International Journal of Circuit Theory and Applications

Year:

2004

Language:

english

File:

PDF, 303 KB

english, 2004

7

Single-electron charging effects in Si MOS devices

D.K. Ferry, M. Khoury, C. Gerousis, M.J. Rack, A. Gunther, S.M. Goodnick

Journal:

Physica E: Low-dimensional Systems and Nanostructures

Year:

2001

Language:

english

File:

PDF, 271 KB

english, 2001

8

The tubulin genes of the human malaria parasite Plasmodium falciparum, their chromosomal location and sequence analysis of the α-tubulin II gene

Stephen P. Holloway, Marina Gerousis, Chris J. Delves, Paul F.G. Sims, John G. Scaife, John E. Hyde

Journal:

Molecular and Biochemical Parasitology

Year:

1990

Language:

english

File:

PDF, 1.21 MB

english, 1990

9

Case study and efficient modelling for variational chemical-mechanical planarisation

Zhang, X., He, L., Gerousis, V., Song, L., Teng, C.-C.

Journal:

IET Circuits Devices & Systems

Year:

2008

Language:

english

File:

PDF, 441 KB

english, 2008

10

Reconfigurable gate array architecture for logic functions in tunneling transistor technology

Gerousis, C., Grepiotis, A.

Journal:

Microelectronics Journal

Year:

2013

Language:

english

File:

PDF, 1.28 MB

english, 2013

11

[IEEE 2008 International Conference on Signals and Electronic Systems - Krakow, Poland (2008.09.14-2008.09.17)] 2008 International Conference on Signals and Electronic Systems - Programmable logic arrays in single-electron transistor technology

Gerousis, Costa, Grepiotis, Arthur

Year:

2008

Language:

english

File:

PDF, 353 KB

english, 2008

12

[IEEE Comput. Soc Design, Automation and Test in Europe. Conference and Exhibition 2001 - Munich, Germany (13-16 March 2001)] Proceedings Design, Automation and Test in Europe. Conference and Exhibition 2001 - C/C ++: progress or deadlock in system-level specification

Villar, E., Gajski, D., Rosenstiel, W., Plantin, J., Cavalloro, P., Gerousis, V., Barton, D.

Year:

2001

Language:

english

File:

PDF, 67 KB

english, 2001

13

[IEEE CICC Custom Integrated Circuits Conference - San Jose, CA, USA (21-24 Sept. 2003)] Proceedings of the IEEE 2003 Custom Integrated Circuits Conference, 2003. - Design and modeling challenges for 90 NM and 50 NM

Year:

2003

Language:

english

File:

PDF, 450 KB

english, 2003

14

[IEEE Comput. Soc 2002 Design, Automation and Test in Europe Conference and Exhibition - Paris, France (4-8 March 2002)] Proceedings 2002 Design, Automation and Test in Europe Conference and Exhibition - Who owns the platform?

Wolf, W., Gerousis, V., Levia, O., Paulin, P., Pinto, M., Rowen, C., Saucier, G.

Year:

2002

Language:

english

File:

PDF, 201 KB

english, 2002

15

[IEEE 2009 International SoC Design Conference (ISOCC) - Busan, Korea (South) (2009.11.22-2009.11.24)] 2009 International SoC Design Conference (ISOCC) - Thermal analysis on a two chip TSS

Gerousis, Vassilios, Fang, Tze-Ting, JinTao Xue,, Garg, Lalit, Tao Li,

Year:

2009

Language:

english

File:

PDF, 197 KB

english, 2009

16

[IEEE Sixth Annual IEEE International ASIC Conference and Exhibit - Rochester, NY, USA (27 Sept.-1 Oct. 1993)] Sixth Annual IEEE International ASIC Conference and Exhibit - New delay model for 0.5μ CMOS ASIC

Gerousis, V., Nghiem Pan,, Weaver, D.

Year:

1993

Language:

english

File:

PDF, 319 KB

english, 1993

17

[ACM Press the 34th annual conference - Anaheim, California, United States (1997.06.09-1997.06.13)] Proceedings of the 34th annual conference on Design automation conference - DAC '97 - Low-power design tools---where is the impact? (panel)

Rabaey, Jan M., Collins, Nanette, Bell, Bill, Frenkil, Jerry, Gerousis, Vassilios, Pedram, Massoud, Singh, Deo, Sproch, Jim

Year:

1997

Language:

english

File:

PDF, 12 KB

english, 1997

18

[ACM Press the 41st annual conference - San Diego, CA, USA (2004.06.07-2004.06.11)] Proceedings of the 41st annual conference on Design automation - DAC '04 - When IC yield missed the target, who is at fault?

Strojwas, Andreas, Campbell, Michael, Gerousis, Vassilios C., Hogan, Jim, Kibarian, John, Levitt, Marc, Ng, Walter, Pramanik, Dipu, Templeton, Mark

Year:

2004

Language:

english

File:

PDF, 93 KB

english, 2004

19

SPIE Proceedings [SPIE SPIE Advanced Lithography - San Jose, California, United States (Sunday 22 February 2015)] Design-Process-Technology Co-optimization for Manufacturability IX - Impact of a SADP flow on the design and process for N10/N7 metal layers

Sturtevant, John L., Capodieci, Luigi, Gillijns, W., Sherazi, S. M. Y., Trivkovic, D., Chava, B., Vandewalle, B., Gerousis, V., Raghavan, P., Ryckaert, J., Mercha, K., Verkest, D., McIntyre, G., Ronse

Year:

2015

Language:

english

File:

PDF, 1.35 MB

english, 2015

20

SPIE Proceedings [SPIE SPIE Advanced Lithography - San Jose, California, USA (Sunday 23 February 2014)] Design-Process-Technology Co-optimization for Manufacturability VIII - Demonstrating production quality multiple exposure patterning aware routing for the 10NM node

Sturtevant, John L., Capodieci, Luigi, Liebmann, Lars, Gerousis, Vassilios, Gutwin, Paul, Zhang, Mike, Han, Geng, Cline, Brian

Year:

2014

Language:

english

File:

PDF, 1.88 MB

english, 2014

21

SPIE Proceedings [SPIE SPIE Advanced Lithography - San Jose, California, United States (Sunday 21 February 2016)] Design-Process-Technology Co-optimization for Manufacturability X - Metal stack optimization for low-power and high-density for N7-N5

Capodieci, Luigi, Cain, Jason P., Raghavan, P., Firouzi, F., Matti, L., Debacker, P., Baert, R., Sherazi, S. M. Y., Trivkovic, D., Gerousis, V., Dusa, M., Ryckaert, J., Tokei, Z., Verkest, D., McIntyr

Year:

2016

Language:

english

File:

PDF, 664 KB

english, 2016

22

SPIE Proceedings [SPIE SPIE Advanced Lithography - San Jose, California, United States (Sunday 26 February 2017)] Design-Process-Technology Co-optimization for Manufacturability XI - Low track height standard cell design in iN7 using scaling boosters

Capodieci, Luigi, Cain, Jason P., Sherazi, S. M. Y., Jha, C., Rodopoulos, D., Debacker, P., Chava, B., Matti, L., Bardon, M. G., Schuddinck, P., Raghavan, P., Gerousis, V., Spessot, A., Verkest, D.,

Year:

2017

Language:

english

File:

PDF, 577 KB

english, 2017

23

SPIE Proceedings [SPIE SPIE Advanced Lithography - San Jose, California, United States (Sunday 26 February 2017)] Design-Process-Technology Co-optimization for Manufacturability XI - Low track height standard-cells enable high-placement density and low-BEOL cost (Conference Presentation)

Capodieci, Luigi, Cain, Jason P., Debacker, Peter, Matti, Luca, Sherazi, Syed M. Y., Baert, Rogier, Gerousis, Vassilios, Nauts, Claire, Raghavan, Praveen, Ryckaert, Julien, Kim, Ryoung-Han, Verkest, D

Year:

2017

Language:

english

File:

PDF, 121 KB

english, 2017

24

[ASEE Conferences 2016 ASEE Annual Conference & Exposition - New Orleans, Louisiana (2016.06.26-2016.07.29)] 2016 ASEE Annual Conference & Exposition Proceedings - Improving Student Retention Through a Redesigned First-Year Engineering Class

Backens, Jonathan, Riedl, Anton, Gerousis, C., Wang, Dali

Year:

2016

Language:

english

File:

PDF, 310 KB

english, 2016

25

Dichotomous Toll-like receptor responses in chronic lymphocytic leukemia patients under ibrutinib treatment

Gounari, Maria, Ntoufa, Stavroula, Gerousi, Marina, Vilia, Maria Giovanna, Moysiadis, Theodoros, Kotta, Konstantia, Papakonstantinou, Nikos, Scarfò, Lydia, Agathangelidis, Andreas, Fonte, Eleonora, Ra

Journal:

Year:

2019

Language:

english

File:

PDF, 1021 KB

english, 2019

26

Identification of miRNAs from stem cell derived microparticles in umbilical cord blood

Xagorari, Angeliki, Gerousi, Marina, Sioga, Antonia, Bougiouklis, Dimitris, Argiriou, Anagnostis, Anagnostopoulos, Achilles, Sotiropoulos, Damianos

Journal:

Experimental Hematology

Year:

2019

Language:

english

File:

PDF, 678 KB

english, 2019

27

Identification of miRNAs from stem cell derived microparticles in umbilical cord blood

Xagorari, Angeliki, Gerousi, Marina, Sioga, Antonia, Bougiouklis, Dimitris, Argiriou, Anagnostis, Anagnostopoulos, Achilles, Sotiropoulos, Damianos

Journal:

Experimental Hematology

Year:

2019

File:

PDF, 678 KB

2019

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